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Low Latency DRAMs
LLDRAM III
RAM Port IP
quad
ddr
sync
 
 
 
 

Low Latency DRAMs (LLDRAM III)
Common I/O

     

GSI's 3rd generation Low Latency DRAM (LLDRAM III) is an ideal solution for advanced data networking applications. It offers an eight-bank memory array architecture for high transaction rates, a reduced pin count address interface, and double data transfers, and is capable of maintaining near-100% bus utilization for many networking tasks. It also offers higher density, lower power, and a lower pin count compared to competing solutions, and the wider data bus (x20 and x40) available in the HSTL versions enables the use of data encoding schemes (e.g., 8b/10b) and ECC protection options (e.g., protecting 32-bit data quantums using 6 or 7 ECC parity bits) that are impractical in traditional x18 and x36 RAMs.

 
 
Part Number Decoder    Part Number Decoder
Common I/O LLDRAM III
Part No.
Org.
Speed (MHz)
Burst Length I/O Type I/O Voltage Core Voltage
Pkg.
Status
Datasheet
GS4303T18/36
64M x 18
36M x 36
600, 500
2 POD 1.2 V, 1.0 V 1.5 V
180-ball micro-BGA
(GN)
In Design
GS4303R18/36
64M x 18
36M x 36
800, 667
4 POD 1.2 V, 1.0 V 1.5 V
180-ball micro-BGA
(GN)
In Design
GS4303TH20/40
64M x 18/20
36M x 36/40
600, 500
2 HSTL 1.2 V 1.5 V
180-ball micro-BGA
(GN)
In Design
GS4303RH20/40
64M x 18/20
36M x 36/40
800, 667
4 HSTL 1.2 V 1.5 V
180-ball micro-BGA
(GN)
In Design

 

 

 

 

 

 
 
 
 
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